1. Field
Example embodiments relate to methods of fabricating semiconductor devices, and more particularly, to methods of fabricating stack type capacitors of semiconductor devices.
2. Description of the Related Art
As semiconductor devices, for example dynamic random access memories (DRAM), achieve higher integration densities, the horizontal area of memory cells within the devices may decrease. As the horizontal area of memory cells decrease, the horizontal area for forming a stack type capacitor included in the memory cell, in which a lower electrode, a dielectric layer, and an upper electrode are stacked, may also decrease.
As the horizontal area for forming a stack type capacitor decreases, cell capacitance may also decrease. When the cell capacitance decreases, the sense margin of a memory cell during reading or writing may decrease and the semiconductor device may not operate satisfactorily at low voltage. Accordingly, various techniques for increasing cell capacitance while decreasing horizontal cell area are being studied.
In order to increase cell capacitance, the thickness of a dielectric layer may be reduced, the surface area of a capacitor may be increased, and/or a dielectric layer having a high dielectric constant may be used. In order to increase the surface area of a capacitor, a cylinder type capacitor including a lower electrode having a 3D shape may be used. However, it may be difficult to deposit a uniform, high quality, high dielectric constant (hereinafter “high k”) dielectric layer with acceptable step coverage on a high aspect ratio feature. For example, it may be difficult to form a reliable high k dielectric layer on the surface of a cylinder type lower electrode. As the integration density of semiconductor devices increases, the thickness of the high k dielectric layer may be reduced and it may become increasingly difficult to form a reliable high k dielectric layer on a cylinder type lower electrode.